Information contained in this application may be related to information contained in commonly assigned, U S. Pat. Nos. 6,261,929, 6,380,108, 6,403,451, 6,486,042, and 6,489,221, and commonly assigned, pending U.S. patent applications Ser. No. 09/736,569 filed Dec. 13, 2000, 09/899,586, filed Jul. 3, 2001, 09/973,383 filed Oct. 9, 2001, 10/115,354 filed Apr. 3, 2002, and 10/115,706 filed Apr. 4, 2002.
1. Field of the Invention
This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor.
2. Background of the Invention
Gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
A major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium nitride layer is grown. Accordingly, although gallium nitride layers have been grown on sapphire substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable.
It also is known to produce low defect density gallium nitride layers by forming a mask on a layer of gallium nitride, the mask including at least one opening that exposes the underlying layer of gallium nitride, and laterally growing the underlying layer of gallium nitride through the at least one opening and onto the mask. This technique often is referred to as xe2x80x9cEpitaxial Lateral Overgrowthxe2x80x9d (ELO). The layer of gallium nitride may be laterally grown until the gallium nitride coalesces on the mask to form a single layer on the mask. In order to form a continuous layer of gallium nitride with relatively low defect density, a second mask may be formed on the laterally overgrown gallium nitride layer, that includes at least one opening that is offset from the underlying mask. ELO then again is performed through the openings in the second mask to thereby overgrow a second low defect density continuous gallium nitride layer. Microelectronic devices then may be formed in this second overgrown layer. ELO of gallium nitride is described, for example, in the publications entitled Lateral Epitaxy of Low Defect Density GaN Layers Via Organometallic Vapor Phase Epitaxy to Nam et al., Appl. Phys. Lett. Vol. 71, No. 18, Nov. 3, 1997, pp. 2638-2640; and Dislocation Density Reduction Via Lateral Epitaxy in Selectively Grown GaN Structures to Zheleva et al, Appl. Phys. Lett., Vol. 71, No. 17, Oct. 27, 1997, pp. 2472-2474, the disclosures of which are hereby incorporated herein by reference.
It also is known to produce a layer of gallium nitride with low defect density by forming at least one trench or post in an underlying layer of gallium nitride to define at least one sidewall therein. A layer of gallium nitride is then laterally grown from the at least one sidewall. Lateral growth preferably takes place until the laterally grown layers coalesce within the trenches. Lateral growth also preferably continues until the gallium nitride layer that is grown from the sidewalls laterally overgrows onto the tops of the posts. In order to facilitate lateral growth and produce nucleation of gallium nitride and growth in the vertical direction, the top of the posts and/or the trench floors may be masked. Lateral growth from the sidewalls of trenches and/or posts also is referred to as xe2x80x9cpendeoepitaxyxe2x80x9d and is described, for example, in publications entitled Pendeo-Epitaxy: A New Approach for Lateral Growth of Gallium Nitride Films by Zheleva et al., Journal of Electronic Materials, Vol. 28, No. 4, February 1999, pp. L5-L8; and Pendeoepitaxy of Gallium Nitride Thin Films by Linthicum et al., Applied Physics Letters, Vol. 75, No. 2, July 1999, pp. 196-198, the disclosures of which are hereby incorporated herein by reference.
ELO and pendeoepitaxy can provide relatively large, low defect gallium nitride layers for microelectronic applications. However, a major concern that may limit the mass production of gallium nitride devices is the growth of the gallium nitride layers on a silicon carbide substrate. Notwithstanding silicon carbide""s increasing commercial importance, silicon carbide substrates still may be relatively expensive compared to conventional silicon substrates. Moreover, silicon carbide substrates generally are smaller than silicon substrates, which can reduce the number of devices that can be formed on a wafer. Moreover, although large investments are being made in silicon carbide processing equipment, even larger investments already have been made in conventional silicon substrate processing equipment. Accordingly, the use of an underlying silicon carbide substrate for fabricating gallium nitride microelectronic structures may adversely impact the cost and/or availability of gallium nitride devices.
The present invention provides methods of fabricating a gallium nitride microelectronic layer by converting a surface of a (111) silicon layer to 3C-silicon carbide. A layer of 3C-silicon carbide is then epitaxially grown on the converted surface of the (111) silicon layer. A layer of 2H-gallium nitride then is grown on the epitaxially grown layer of 3C-silicon carbide. The layer of 2H-gallium nitride then is laterally grown to produce the gallium nitride microelectronic layer.
In one embodiment, the silicon layer is a (111) silicon substrate, the surface of which is converted to 3C-silicon carbide. In another embodiment, the (111) silicon layer is part of a Separation by IMplanted OXygen (SIMOX) silicon substrate which includes a layer of implanted oxygen that defines the (111) layer on the (111) silicon substrate. In yet another embodiment, the (111) silicon layer is a portion of a Silicon-On-Insulator (SOI) substrate in which a (111) silicon layer is bonded to a substrate. Accordingly, the present invention can use conventional bulk silicon, SIMOX and SOI substrates as a base or platform for fabricating a gallium nitride microelectronic layer. By using conventional silicon technology, low cost and/or large area silicon substrates may be used and conventional silicon wafer processing systems also may be used. Accordingly, low cost and/or high volume production of gallium nitride microelectronic layers may be provided.
The surface of the (111) silicon layer preferably is converted to 3C-silicon carbide by chemically reacting the surface of the (111) silicon layer with a carbon containing precursor such as ethylene, to convert the surface of the (111) silicon layer to 3C-silicon carbide. The layer of 3C-silicon carbide then may be epitaxially grown on the converted surface using standard vapor phase epitaxial techniques for silicon carbide. Alternatively, the layer of 3C-silicon carbide may be grown directly on the (111) silicon layer, without the need for conversion. The epitaxially grown layer of 3C-silicon carbide may be thinned. Prior to growing the layer of gallium nitride, an aluminum nitride and/or gallium nitride buffer layer preferably is grown on the epitaxially grown layer of 3C-silicon carbide. The gallium nitride then is grown on the buffer layer, opposite the epitaxially grown layer of 3C-silicon carbide.
Lateral growth of the layer of 2H-gallium nitride may be performed by ELO wherein a mask is formed on the layer of 2H-gallium nitride, the mask including at least one opening that exposes the layer of 2H-gallium nitride. The layer of 2H-gallium nitride then is laterally grown through the at least one opening and onto the mask. A second, offset mask also may be formed on the laterally grown layer of 2H-gallium nitride and a second laterally grown layer of 2H-gallium nitride may be overgrown onto the offset mask. Lateral growth of the layer of 2H-gallium nitride also may be performed using pendeoepitaxial techniques wherein at least one trench and/or post is formed in a layer of 2H-gallium nitride to define at least one sidewall therein. The layer of 2H-gallium nitride then is laterally grown from the at least one sidewall. Pendeoepitaxial lateral growth preferably continues until the laterally grown sidewalls coalesce on the top of the posts or trenches. The top of the posts and/or the trench floors may be masked to promote lateral growth and reduce nucleation and vertical growth. The trenches preferably extend into the silicon carbide layer to also reduce nucleation and vertical growth.
As described above, the present invention can use bulk silicon substrates, SIMOX substrates or SOI substrates as a platform for gallium nitride fabrication. Preferred methods using each of these substrates now will be described.
When using a (111) silicon substrate, the surface of the (111) silicon substrate preferably is converted to 3C-silicon carbide and a layer of 3C-silicon carbide then is epitaxially grown on the converted surface of the (111) silicon substrate. The epitaxially grown layer of 3C-silicon carbide may be thinned. An aluminum nitride and/or gallium nitride buffer layer is grown on the epitaxially grown layer of 3C-silicon carbide. A layer of 2H-gallium nitride is grown on the buffer layer. The layer of 2H-gallium nitride then is laterally grown to produce the gallium nitride microelectronic layer. The lateral growth may proceed using ELO, pendeoepitaxy and/or other techniques.
When using a SIMOX substrate, oxygen is implanted into a (111) silicon substrate to form a buried silicon dioxide layer that defines a (111) silicon surface layer on the (111) silicon substrate. At least a portion of the (111) silicon surface layer, and preferably all of the (111) silicon surface layer, is converted to 3C-silicon carbide. A layer of 3C-silicon carbide then is epitaxially grown on the converted (111) silicon surface layer. The epitaxially grown layer of 3C-silicon carbide then may be thinned and an aluminum nitride and/or gallium nitride buffer layer is grown on the epitaxially grown layer of 3C-silicon carbide. A layer of 2H-gallium nitride then is grown on the buffer layer. The layer of 2H-gallium nitride then is laterally grown, using ELO, pendeoepitaxy and/or other techniques to produce the gallium nitride microelectronic layer.
Finally, when using an SOI substrate, a (111) silicon substrate is bonded to another substrate, preferably a (100) silicon substrate. The (111) silicon substrate is thinned to define a (111) silicon layer on the (100) silicon substrate. At least a portion, and preferably all, of the (111) silicon layer is converted to 3C-silicon carbide. A layer of 3C-silicon carbide is epitaxially grown on the converted (111) silicon layer. The epitaxially grown layer of 3C-silicon carbide may be thinned and an aluminum nitride and/or gallium nitride buffer layer is grown on the epitaxially grown layer of 3C-silicon carbide. A layer of 2H-gallium nitride then is grown on the buffer layer and the layer of 2H-gallium nitride is laterally grown, using ELO, pendeoepitaxy and/or other techniques to produce the gallium nitride microelectronic layer. When using SOI substrates, microelectronic devices also may be formed in the (100) silicon substrate, prior to or after forming the gallium nitride microelectronic layer. A portion of the (111) silicon layer, the 3C-silicon carbide layer, the gallium nitride layer and the gallium nitride microelectronic layer may be removed to expose the microelectronic devices in the (100) silicon substrate. Alternatively, an epitaxial silicon layer may be grown from the exposed portion of the (100) silicon substrate, and microelectronic devices may be formed in the epitaxial silicon layer. The gallium nitride structures may be capped prior to forming the epitaxial silicon layer. Thus, for example, optoelectronic devices may be formed in the gallium nitride layer whereas conventional CMOS or other microelectronic devices may be formed in the (100) silicon substrate. Integrated optoelectronic substrates thereby may be formed.
In general, gallium nitride microelectronic structures according to the present invention preferably comprise a (111) silicon layer, a 3C-silicon carbide layer on the (111) silicon layer, an underlying layer of 2H-gallium nitride on the 3C-silicon carbide layer and a lateral layer of 2H-gallium nitride on the underlying layer of 2H-gallium nitride. The (111) silicon layer may comprise a surface of a (111) bulk silicon substrate, a surface of a (111) SIMOX substrate or a surface of a (111) SOI substrate. A buffer layer of aluminum nitride and/or gallium nitride may be provided between the 3C-silicon carbide layer and the underlying layer of 2H-gallium nitride. A mask may be provided on the underlying layer of 2H-gallium nitride, the mask including at least one opening that exposes the underlying layer of 2H-gallium nitride, and the lateral layer of 2H-gallium nitride extending through the at least one opening and onto the mask. A second laterally offset mask and a second lateral layer of 2H-gallium nitride also may be provided. Alternatively or in addition, at least one trench and/or post may be provided in the underlying layer of 2H-gallium nitride that defines at least one sidewall in the underlying layer of 2H-gallium nitride, and the lateral layer of 2H-gallium nitride may extend from the at least one sidewall. The lateral layer of 2H-gallium nitride may extend onto the post tops, which may be masked or unmasked. The trench bottoms also may be masked or the trench may extend through the aluminum nitride layer into the silicon carbide layer.
A preferred embodiment using a (111) bulk silicon substrate includes a 3C-silicon carbide layer on the (111) silicon substrate, a buffer layer of aluminum nitride and/or gallium nitride on the 3C-silicon carbide layer, an underlying layer of 2H-gallium nitride on the buffer layer and a lateral layer of 2H-gallium nitride on the underlying layer of 2H-gallium nitride. A preferred embodiment using a SIMOX substrate includes a (111) silicon substrate, a silicon dioxide layer on the (111) silicon substrate, a 3C-silicon carbide layer on the silicon dioxide layer, a buffer layer of aluminum nitride and/or gallium nitride on the 3C-silicon carbide layer, an underlying layer of 2H-gallium nitride on the buffer layer and a lateral layer of 2H-gallium nitride on the underlying layer of 2H-gallium nitride. Finally, a preferred embodiment using an SOI substrate includes a (100) silicon substrate, an insulating layer on the (100) silicon substrate, a 3C-silicon carbide layer on the insulating layer, a buffer layer of aluminum nitride and/or gallium nitride on the 3C-silicon carbide layer, an underlying layer of 2H-gallium nitride on the buffer layer and a lateral layer of 2H-gallium nitride on the underlying layer of 2H-gallium nitride. A plurality of microelectronic devices preferably are formed in the (100) silicon substrate. The 3C-silicon carbide layer, the layer of aluminum nitride, the underlying layer of 2H-gallium nitride and the lateral layer of 2H-gallium nitride preferably define a pedestal that exposes the plurality of microelectronic devices in the (100) silicon substrate. Alternatively, the pedestal may expose the (100) silicon substrate, substrate, a (100) silicon layer may be included on the exposed portion of the (100) silicon substrate, and the microelectronic devices may be formed in the (100) silicon layer. In all of the above embodiments, a layer of (111) silicon may be present between the insulating layer and the 3C-silicon carbide layer. Accordingly, gallium nitride microelectronic structures may be formed on commonly used bulk silicon, SIMOX and SOI substrates. Low cost and/or high availability gallium nitride devices thereby may be provided. Integration with conventional CMOS or other silicon technologies also may be facilitated.